Thursday, June 13, 2002, 8:30 AM - 10:00 AM | Room: 292 SESSION 38    Routing and Buffering    Chair: Noel Menezes - Inte Corp., Hillsboro, OR    Organizers: Charles J Alpert, Steven Teig    Buffering is a key aspect of interconnect design. It is crucial to meld routing and timing into a consistent framework for timing closure. This session covers a range interconnect performance issues such as efficient interconnect synthesis, buffer planning with pin assignment, and implementation issues in global routing data structures.      38.1 S-Tree: A Technique for Buffered Routing Tree Synthesis    Speaker(s): Milos Hrkic - Univ. of Illinois, Chicago, IL    Author(s): Milos Hrkic - Univ. of Illinois, Chicago, IL John Lillis - Univ. of Illinois, Chicago, IL      38.2 An Algorithm for Integrated Pin Assignment and Buffer Planning    Speaker(s): Hua Xiang - Univ. of Texas, Austin, TX    Author(s): Hua Xiang - Univ. of Texas, Austin, TX Xiaoping Tang - Univ. of Texas, Austin, TX D. F. Wong - Univ. of Texas, Austin, TX      38.3 An Efficient Routing Database    Speaker(s): Narendra V. Shenoy - Synopsys, Inc., Bangalore, India    Author(s): Narendrea V. Shenoy - Synopsys, Inc., Bangalore, India William Nicholls - Synopsys, Inc., Mountain View, CA